The disclosed embodiments of the present invention relate to changing a clock frequency of a clock signal used by a clock-driven device, and more particularly, to an apparatus and method for controlling a controllable clock source to generate a clock signal with a frequency transition under a condition that the controllable clock source stays in a frequency-locked state.
A memory device is a key component of an electronic device. For example, the memory device may include a dynamic random access memory (DRAM) used to buffer instructions and data. The computational workload of the electronic device is not always high. If the memory device is operated at a highest clock frequency under a normal mode, this would result in higher power consumption. The conventional power management design may change the clock frequency of the memory clock when the computational workload of the electronic device is lower than a threshold. The reduced clock frequency also enables the supply voltage to be reduced, which decreases power consumption and extends battery life (if the electronic device is a portable device powered by a battery).
In general, the memory clock is generated from a clock generator, such as a phase-locked loop (PLL). When the clock frequency of the memory device is allowed to be reduced, the memory controller controls the memory device to enter a self-refresh mode, and then adjusts the PLL so as to change the clock frequency of the memory clock. However, when an input of the PLL has a significant frequency change, the memory clock generated from the clock generator may fail to swiftly track the frequency variation of the PLL input. Thus, the PLL leaves a frequency-locked state. The generation of the memory clock is not stable until the PLL enters the frequency-locked state again. However, the PLL needs a period of time to enter the frequency-locked state again to provide a stable memory clock with the reduced clock frequency. As a result, the system is unable to access the memory device before the PLL provides a stable memory clock with the reduced clock frequency and the memory device leaves the self-refresh mode. If there is a real-time task that needs to access the memory device at a moment that access of the memory device is unavailable due to frequency change, the real-time task fails to work normally, which may lead to system malfunction.